1. Field of the Invention
The present invention relates to a low pass filter circuit in a semiconductor integrated circuit, and a voltage regulator including the low pass filter circuit.
2. Description of the Related Art
In an electronic device equipped with a high frequency circuit or a wireless device, a low noise power supply is required, and hence a low-dropout (LDO) voltage regulator having good noise characteristics is used. Primary factors of output noise of the voltage regulator include 1/f noise generated in an internal reference voltage circuit and resistor thermal noise generated in a resistor voltage dividing circuit for determining an output voltage. In recent years, following the demand for extended operating time of mobile electronic devices, there is an increasing tendency to use a CMOS transistor integrated circuit having smaller current consumption than a bipolar transistor integrated circuit. However, it is known that the CMOS transistor circuit has larger 1/f noise than the bipolar transistor circuit. It is therefore required to suppress noise of a voltage regulator in the CMOS transistor circuit. It is generally considered that the 1/f noise depends on an interfacial effect in a channel of a MOS transistor, and the 1/f noise is large in a low frequency region. In order to obtain a lower noise voltage, it has been known to use a configuration in which a low pass filter circuit is connected to an output of an internal reference voltage circuit (see Japanese Patent Application Laid-open No. Hei 05-127761). However, the 1/f noise is large in a low frequency region, and hence, in order to sufficiently suppress noise by the low pass filter circuit, it is necessary to set a cutoff frequency to be very low, for example, about several Hz to several tens of Hz.
First, a conventional low pass filter circuit is described. FIG. 4 is a diagram illustrating a voltage regulator including the conventional low pass filter circuit.
The voltage regulator including the conventional low pass filter circuit includes a ground terminal 100, a power supply terminal 101, an output terminal 102, a low pass filter circuit 403, an amplifier 105, an output transistor 106, and a reference voltage generation circuit 407 (see, for example, U.S. Pat. No. 7,397,226).
Next, the operation of the voltage regulator including the conventional low pass filter circuit is described.
In the reference voltage generation circuit 407, an amplifier 104 controls a voltage of a gate terminal of a PMOS transistor 120 so that an output voltage Vref of a reference voltage source 108 and a divided voltage Vfb obtained by dividing the output voltage Vref by resistors 151 and 152 are equal to each other. Vfb and Vref are equal to each other, and hence, when the resistance values of the resistor 151 and 152 are represented by R1 and R2, respectively, a voltage Vref2 of a drain terminal of the PMOS transistor 120 is determined by a voltage dividing ratio of R1 and R2 as expressed by Expression (1)Vref2=Vref·(R1+R2)/R2  (1)
In general, in an integrated circuit, the fluctuations in absolute value of resistive elements are large. However, the resistance ratio can be set relatively accurately, and hence, by adjusting the resistance ratio of the resistors 151 and 152, the voltage Vref2 can be accurately set to an arbitrary value. A voltage of an input terminal 112 and a voltage of an output terminal 113 of the low pass filter circuit 403 are equal to each other in the steady state, and hence a voltage of the an inverting input terminal of the amplifier 105 is equal to the reference voltage Vref2.
The amplifier 105 controls a voltage of a gate terminal of the output transistor 106 so that the voltage of the output terminal 113 of the low pass filter circuit 403 and a voltage Vout of the output terminal 102 of the voltage regulator are equal to each other. Therefore, the output voltage Vout becomes equal to Vref2. As described above, Vref2 is determined by the resistance ratio of the resistors 151 and 152, and hence the output voltage Vout can be arbitrarily adjusted through the adjustment of the resistance ratio of the resistors.
Next, the operation of the low pass filter circuit is described. A current source 111 is designed so as to cause a very small current I1 of, for example, about sub-nA to several nA, to flow. The current I1 is equal to a drain current of a PMOS transistor 122, and hence the PMOS transistor 122 operates in the weak inversion region and has a very large ON-state resistance of, for example, about several hundreds of MΩ. An ON-state resistance Ron of a PMOS transistor 121 which is current-mirror connected to the PMOS transistor 122 is similarly very large. Thus, a cutoff frequency fc of a low pass filter determined by the ON-state resistance Ron and a capacitor 161 is very low.
The low pass filter circuit 403 suppresses 1/f noise which is contained in the reference voltage Vref2 and generated in the reference voltage generation circuit 407 and thermal noise which is generated in the resistor voltage dividing circuit of the resistors 151 and 152. Thus, smaller noise appears in the output terminal 102. Therefore, a voltage regulator with small output noise can be obtained.
In the voltage regulator including the conventional low pass filter circuit, at high temperature, the output voltage shifts due to a substrate leakage current of the PMOS transistor.
In the PMOS transistor, parasitic diodes are formed between p-type conductive source, channel, and drain regions and an n-type conductive well. Then, a thermo-stimulated current flows in the forward direction of the diodes. The thermo-stimulated current increases exponentially with an increase in temperature, and hence the forward current becomes larger at a higher temperature. In the PMOS transistor, holes flow into the n-type conductive well due to the forward current. The holes flowing into the n-type conductive well flow to the ground via a parasitic reverse diode formed between the well and a p-type conductive substrate, or alternatively the holes are recombined with electrons as major carriers in the n-type conductive well and disappear to generate a recombination current, which becomes a substrate leakage current in total. In particular, when the PMOS transistor is operated in the weak inversion region in order to reduce a cutoff frequency of the low pass filter circuit enough, a potential difference between the channel region and the well becomes smaller than a potential difference between the source and the well, and hence the substrate leakage current from the channel region increases. In the conventional circuit, the potential of the input terminal of the low pass filter, that is, the source potential of the PMOS transistor of the low pass filter is controlled to be constant. However, when a leakage current flows from the channel region, the potentials of the channel and the drain are decreased. When the drain potential decreases, the output voltage of the low pass filter circuit decreases, and hence the output voltage of the voltage regulator also decreases along with the operation of the voltage regulator.
The mechanism for holes has been described above, but the same holds true for electrons.